Make file is a small tool used for building programs which needs modules.For example ,I have a program called “MyMain.c” which contains two header file “alfa.h” and “beta.h” the definitions are “alfa.c” and “beta.c” respectively . In order to compile this  run the following command

gcc -o output MyMain.c alfa.c beta.c

it will create a binary called output by using the object files of Mymain.c,alfa.c and beta.c.If your using IDE like eclipse or Qt,it will take care of all these commands.But in case of manual compiling you have to type these commands every time.Here is the use of makefiles.you can write all the above command and put it in  a file named “makefile”  and just run make command to compile,done!.

The make file goes through each of the files mentioned in the make file and check for any changes and recompile only those files.The makefile for above example is

output:MyMain.o alfa.o beta.o
        cc -o output MyMain.o alfa.o beta.o
MyMain.o:MyMain.c alfa.h beta.h
        cc -c myMain.c
alfa.o:alfa.c alfa.h
        cc -c alfa.c
beta.o:beta.c beta.h
        cc -c beta.c

In addition to this, makefile can have some intelligence  to make things much faster and efficient.For that there are syntax and rules for creating make file.


Makefile rule syntax

target:prerequisites
    recipe
    ..
    ..

Rule for makefile will be look like this

target: is the name of the file or action generated by program.In our example output,mymain.o,alfa.o,beta.o are targets.

prerequisites:are the inputs used to create the targets.eg:mymain.o ,alfa.o,beta.o are the prerequisites for output.

recipe:is the command performed by make.NB:there should be a tab space before every recipe line


Variables in makefile

Variables can be used for simplify the makefile.Defined variable can be accessed  by $(variable_name) .Variables will helps to reduce the typo errors in big complex makefiles and allows to make changes in files without changing each places.Eg:The above make file can be further reduced

objects =MyMain.o alfa.o beta.o
headers =alfa.h beta.h

output:$(objects)
      cc -o output $(objects)
 
MyMain.o:$(headers)
 
alfa.o:alfa.h

beta.o:beta.h

Here the ‘.o‘ targets are further reduced by exploiting the implicit rules of make.ie  the make will generate .o file from its corresponding .c file without explicitly mentioning cc -c command.


PHONY targets

which are the additional actions inside the make file executed on explicit request.

objects =MyMain.o alfa.o beta.o
headers =alfa.h beta.h

output:$(objects)
 cc -o output $(objects)
 
MyMain.o:$(headers)
 
alfa.o:alfa.h

beta.o:beta.h

.PHONY clean
clean :
      -rm output $(objects)

the files created by make commands can be cleared by running clear PHONY on running

make clean

Conclusion

This is very small tuto to the makefiles.But this is fair enough to deal with makefiles for small small uses.As of now  im winding up this tuto here and will post about advanced makefile tutorial soon.:)

 

Advertisements